Band-to-Band Tunnel Field-Effect Transistor with Graded Semiconductor Heterostructure at the Tunnel Junction and Method for Its Manufacture

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This patent describes a novel design and fabrication method for a band-to-band tunneling field-effect transistor (TFET) that uses a graded semiconductor heterostructure at the tunneling junction. The core innovation is creating a thin region where the concentration of a material with a smaller band gap (such as Ge) initially rises, reaches a maximum, and then falls, all within a host material with a larger band gap (such as Si). This arrangement improves tunneling efficiency, enables better subthreshold performance, and is easier to fabricate defect-free due to the reduced need for thick mismatched layers.

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• Low-power and high-efficiency transistors for mobile devices, laptops, and Internet-of-Things (IoT) sensors.
• Advanced integrated circuits (ICs) for high-performance processors in computers and servers.
• Ultra-dense nanoelectronics for data centers and future memory/storage technologies requiring reduced heat and power loss.
• Specialized logic devices and circuits where extremely steep switching slopes and reduced leakage are crucial, such as battery-powered medical implants or wearables.
• Emergent quantum and analog computing circuits requiring superior threshold control and low energy consumption.

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• Greatly reduced power consumption thanks to steep subthreshold slope (< 60 mV/dec), enabling lower supply voltages.
• Minimized fabrication defects due to the graded, thin heterojunction, allowing easier manufacturing and reliable monocrystalline growth.
• Lower leak currents compared to traditional MOSFETs, resulting in higher energy efficiency and less unwanted heat.
• Flexible material systems (e.g., Si-Ge, GaAs-InGaAs) that can be tuned for optimal performance and compatibility with semiconductor industry standards.
• Potential for higher current drive thanks to enlarged tunneling areas in planar and vertical (nanowire/FinFET) device designs.

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Patent Abstract

A band-to-band tunnelling field effect transistor has been developed in the context of the invention. This transistor consists of doped source, doped drain and undoped channel in a p-i-n structure. The channel is adjoined by a dielectric that separates a gate for controlling the transistor from the channel. Between the undoped channel and the adjoining doped region, the tunnel junction is formed by a graded heterostructure composed of at least a first material (A) and a second material (B) having a larger band gap. According to the invention, along the heterostructure, the concentration of material (A) firstly rises, assumes a maximum and then falls again. It has been recognized that only a very thin layer of the material (A) is required for such a structure, with the result that the critical layer thickness for defect-free monocrystalline growth does not have to be exceeded or has to be exceeded much less than in the graded Si/Ge heterostructure according to the prior art.