Method for Capacitive Readout of Resistive Memory Elements and Non-Volatile, Capacitively Readable Memory Elements for Performing the Method

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This patent describes a method for reading non-volatile memory elements that use resistive memory cells by leveraging capacitance differences between their states (0 and 1) instead of current-based readout. By connecting a fixed, state-independent capacitance (such as that of a DRAM capacitor or the gate dielectric of a transistor) in series with the resistive memory cell, the device can be read out via capacitive means. This approach simplifies memory design, allows non-destructive reading, and supports compact, cost-effective non-volatile memory elements, including those compatible with modern transistor and DRAM structures.

Use CasesContent extracted from patent full text and abstract with AI.

• Non-volatile memory modules for computers and embedded devices
• High-density memory chips for consumer electronics
• Memory arrays for IoT, mobile, and industrial sensors that need data retention without power
• Next-generation data storage devices requiring quick, non-destructive read operations
• Hybrid memory chips combining DRAM speed and non-volatile storage
• Resistive RAM (ReRAM) solutions in artificial intelligence and neuromorphic hardware
• Secure memory elements for cryptographic or authentication applications

BenefitsContent extracted from patent full text and abstract with AI.

• Allows non-destructive reading of resistive memory (no need to rewrite after each read)
• Simplifies manufacturing by removing the need for pairs of differently fabricated memory cells
• Reduces memory footprint and cost by eliminating redundant cells and using simple capacitive structures
• Increases signal strength and reliability of capacitively-read resistive memory
• Enables integration with existing DRAM and transistor (CMOS) technology for versatile applications
• Potential for higher density and improved scalability in memory arrays
• Enhanced compatibility with circuit-level optimization and multi-state (multi-bit) storage

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Inventors & Applicants

Patent Abstract

Within the scope of the invention, a method for reading a nonvolatile memory element having at least two stable states 0 and 1 has been developed. Said memory element comprises at least one resistive memory cell, which encodes the two states 0 and 1 to give a state HRS with a relatively high electrical resistance and a state LRS with a relatively low electrical resistance. The memory element has different capacitances C0.1 in the two states 0 and 1; this difference is used to determine which state is present. In accordance with the invention, a memory element is selected in which a fixed capacitance, which is independent of the state of the memory cell, is connected in series with the memory cell. It has been identified that a series circuit comprising a resistive memory cell and a fixed capacitance instead of a second resistive memory cell improves the signal strength during capacitive reading. It has also been identified that the second memory cell is not required for the memory function when the memory element is read capacitively. Within the scope of the invention, in addition memory elements have been developed which combine a field-effect transistor or a DRAM structure with a resistive memory cell or an antiseries series circuit of such memory cells. Such memory elements are particularly suitable for implementing the method according to the invention.