Method for Electrical Testing of Electronic Components of an Integrated Circuit
Simple SummaryContent extracted from patent full text and abstract with AI.
This invention relates to a method for electrically testing electronic components of an integrated circuit using a combined SEM (Scanning Electron Microscope) and AFM (Atomic Force Microscope) nanoprober. The process involves first imaging non-sensitive (non-target) regions with the SEM for fast navigation and tip placement, then switching to the AFM to precisely image and characterize sensitive (target) areas where actual electrical measurements are carried out, thereby avoiding electron beam-induced damage to sensitive device regions.
Use CasesContent extracted from patent full text and abstract with AI.
- Failure analysis of semiconductor devices in the electronics industry
- Quality control and reliability assessment during integrated circuit manufacturing
- R&D and process optimization in semiconductor fabrication
- Detailed electrical probing and diagnostics on highly miniaturized or sensitive circuit regions
- Characterization and investigation of new nanoelectronic device structures
BenefitsContent extracted from patent full text and abstract with AI.
- Minimizes the risk of electron beam-induced damage to sensitive electronic components during testing
- Combines the speed and wide field-of-view of SEM with the precision and non-destructive capabilities of AFM
- Allows for accurate electrical measurements in regions that are otherwise vulnerable to conventional SEM-based methods
- Enhances the effectiveness of failure analysis and fault localization in micro- and nanoelectronics
- Supports improved yield and reliability in semiconductor manufacturing by enabling safer, high-precision diagnostic procedures
Technical Classifications (CPCs)
Main Classifications
Electrical & Electronic Tech
Physics & Measurement
Sub Classifications
Electric Elements
Measuring & Testing
CPC Codes
Inventors & Applicants
Inventors
Applicants
Forschungszentrum Juelich Gmbh
Patent Abstract
The invention relates to a method for electrically examining electronic components of an integrated circuit. According to the invention, a method for electrically examining electronic components of an integrated circuit (1) is provided, comprising a target region (3) to be examined, in which electronic components having contact points (5) are located, and a residual region referred to as non-target region (2), in which an examination is carried out using a combined SEM/AFM nanaprobe. In a first step, the non-target region (2) is at least partially imaged with the scanning electron microscope part of the SEM/AFM nanaprobe, and in a subsequent step, the target region (3) is at least partially imaged with the scanning force microscope part of the SEM/AFM nanaprobe.
Key Information
Publication No.
DE102018009623A1
Family ID
68696188
Publication Date
2020-06-10
Application No.
DE102018009623A
Application Date
2018-12-07
Priority Date
2018-12-07
Granted
Yes (2/8)
Possible Cooperation
For further information please contact the transfer office.