Memory element selecting method, involves encoding states of memory element in stable conditions, respectively, and selecting variable, where cell in one of states carries out respective contributions than another cell in other state

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The patent describes a method for nondestructively reading the state of resistive memory elements that are made up of at least two serially connected memory cells. By carefully selecting and measuring specific electrical properties such as voltage or capacitance, it is possible to determine the logic state (0 or 1) of the memory element without causing any change to the memory state (i.e., without 'consuming' or erasing the data during the read operation). The memory element itself is designed so that the constituent cells contribute differently to these measurements depending on their physical states, enabling reliable differentiation between data states.

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• Non-volatile memory chips in computers and mobile devices where frequent read operations are required
• High-density memory arrays in data centers and server environments
• Memory elements in devices for industrial automation, IoT, or embedded systems that require reliable and long-term data storage
• Scientific instrumentation needing robust, long-lifetime memory components
• Advancement of new memory technology to compete with or complement Flash, DRAM, or similar memory types

BenefitsContent extracted from patent full text and abstract with AI.

• Enables truly nondestructive readout, preserving written data after each read and increasing the longevity of memory cells
• Reduces wear-out and degradation commonly associated with frequent rewriting in memory arrays
• Improves energy efficiency by eliminating mandatory rewrite cycles after reading
• Allows construction of much larger and denser memory arrays than conventional methods, due to minimal parasitic effects and robust readout scheme
• Supports faster data access times due to reduced need for refresh cycles and less error recovery
• Enables new types of memory architectures with improved reliability and endurance

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Patent Abstract

The method involves encoding state 0 of a memory element in stable conditions A1 and B0, and encoding state 1 of the memory element in stable conditions A0 and B1 by measurement of an electrical variable e.g. voltage (V) and capacitance (CA), of a series circuit. The electrical variable is selected, where a memory cell (A) in the state A0/A1 carries out respective contributions than another memory cell (B) in the state B0/B1. Alternating voltage drop (Vmess) is measured over the memory element, where the memory element is designed as a layer of active material. An independent claim is also included for a memory element.