Device and Method Based on Memristive Domino Processing Unit-Based Computing Paradigms

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This invention describes a novel computing device and method that use memristor-based domino processing units, enabling an advanced computer architecture that efficiently combines memory and processing tasks. Instead of separating computation and memory like traditional von Neumann computers, this approach leverages memristors to execute sequences of logic and memory operations inside memory, using various innovative logic modes (MIMO, VIMO, MIVO, VIVO). It enables flexible, energy-efficient, and low-latency data processing suitable for large-scale, real-time applications.

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• Edge computing for Internet of Things (IoT) devices, where low power and real-time in-memory processing are critical.
• Big data analytics and real-time data extraction tasks in data centers.
• Artificial intelligence (AI) and machine learning acceleration, especially for applications benefitting from in-memory computing.
• Low-power portable and embedded systems in consumer electronics and wearables.
• Accelerated search and pattern matching in databases or network security.
• Sensor data fusion and preprocessing in smart sensor networks.

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly reduces data transfer between memory and processing units, overcoming the 'memory wall' limitation.
• Improves computational speed and energy efficiency compared to traditional architectures.
• Enables real-time, large-scale data processing and analytics within the memory array itself.
• Flexible operation by supporting various logic and processing modes (MIMO, VIMO, MIVO, VIVO), adaptable to different application needs.
• Areas and latency are optimized through automatic operation sequence synthesis and efficient cell mapping.
• Reduces hardware footprint and power consumption, making it ideal for edge devices and portable systems.
• Supports universal logic computation without dedicated logic gate architectures, enabling broad applicability.

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Patent Abstract

The invention relates to an apparatus according to one embodiment. The apparatus comprises a control unit (110) and a memory unit (120). The memory unit (120) comprises a memory which has a plurality of memristors. The control unit (110) is designed to perform a sequence of processing steps. A first processing step of the sequence of processing steps, with which the sequence of processing steps begins, is a first of two or more MIMO processing steps. A final processing step of the sequence of processing steps, with which the sequence of processing steps ends, is another of the two or more MIMO processing steps. The sequence of processing steps also comprises one or more MIVO processing steps. Furthermore, the sequence of processing steps has one or more VIMO processing steps. In each MIMO processing step of the two or more MIMO processing steps, the control unit (110) is designed to obtain an input of the MIMO processing step by reading out memory contents of one of the plurality of memristors, and to store an output of the MIMO processing step in one of the plurality of memristors. Furthermore, in each VIMO processing step of the one or more VIMO processing steps, the control unit (110) is designed to obtain an input of the VIMO processing step by evaluating an input voltage, and to store an output of the VIMO processing step in one of the plurality of memristors. Furthermore, in each MIVO processing step of the one or more MIVO processing steps, the control unit (110) is designed to obtain an input of the MIVO processing step by reading out the memory contents of one of the plurality of memristors, and to output an output of the MIVO processing step as an output voltage.