Method and Apparatus for Generating a Random Number

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This invention is a hardware random number generator that exploits the naturally noisy, unpredictable resistance fluctuations of a memristor (specifically a VCM-type memristor) to produce true randomness. A single fluctuating analog signal is compared with a time-delayed version of itself; each comparison yields one random bit (0 or 1). The resulting bit stream is then passed through two successive digital processing stages — an XOR gate clocked at a higher frequency and a non-linear feedback shift register (NLFSR) clocked at an even higher frequency — to increase both the output bit rate and the unpredictability of the final random number. The three-stage, escalating-frequency pipeline produces binary random numbers that pass standard cryptographic quality tests such as the NIST test suite.

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• Generating cryptographic keys for hardware security modules (HSMs) in banking and financial infrastructure.
• Providing a true random seed source for embedded security chips in IoT devices and smart cards.
• Supplying unpredictable nonces and session tokens for TLS/SSL handshake protocols in network equipment.
• Enabling secure key generation in automotive electronic control units (ECUs) that require tamper-resistant randomness.
• Supporting Monte Carlo simulations and stochastic computing in scientific or AI accelerator hardware where high-throughput random bit streams are needed.
• Serving as an on-chip entropy source in system-on-chip (SoC) designs for mobile processors or FPGAs.

BenefitsContent extracted from patent full text and abstract with AI.

• Uses a single memristor and a simple RC delay circuit as the entropy source, keeping hardware complexity and chip area very low compared to multi-component true random number generators.
• The three-stage pipeline with escalating clock frequencies (comparator → XOR gate → NLFSR) significantly increases the output bit rate beyond what the physical noise source alone could deliver.
• Cascading different processing methods (analog comparison, XOR, non-linear shift register) at different frequencies makes the output extremely difficult to predict even if the raw analog signal is observed.
• VCM memristors exhibit inherent stochastic resistance switching combined with thermal noise, providing a high-quality physical entropy source that passes NIST statistical randomness tests.
• The architecture requires only one physical measurement channel (the signal is self-delayed), reducing component count and calibration effort compared to dual-source designs.
• The non-linear feedback shift register stage further decorrelates the bit stream, hardening the generator against reverse-engineering or side-channel analysis.

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Patent Abstract

[0001] The invention relates to a method for generating a random number with the steps: a first input signal (I(t)) is generated that changes randomly with time (t), a second input signal (I(t+Δt)) is generated that changes randomly with time, the first input signal (I(t)) is compared with the second input signal (I(t+Δt)), depending on the result of the comparison, either a first logical 0 or a first logical 1 is generated and thus a first bit of a binary random number, after generating the first bit of the binary random number, the steps are repeated multiple times to generate further bits of the binary random number. [0002] The invention further relates to a random number generator for generating a random number according to the claimed method with a memristor and a measuring device for reading out a resistance value of the memristor to generate an input signal (I(t)) that changes randomly with time. The random number generator comprises a delay device (2) that temporally delays the generated input signal (I(t)), a comparator (1) that compares the input signal (I(t)) with the temporally delayed input signal (I(t+Δt)) and that generates bits of a first random number according to a first frequency through comparisons. The random number generator comprises a first processing device (3) that converts bits of the first generated random number according to a second frequency (CLK 1) into bits of a second random number, and a second processing device (4) that converts bits of the second generated random number according to a third frequency (CLK 2) into bits of a third random number. The first frequency is smaller than the second frequency (CLK 1). The second frequency (CLK 1) is smaller than the third frequency (CLK 2).