Substrate's e.g. wafer, plated-through hole and strip conductor producing method, involves producing plated-through hole and strip conductor simultaneously on one side of substrate by further deposition of metal

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent describes a method for manufacturing substrates (such as semiconductor wafers, PCBs, or chips) that enables the simultaneous production of plated-through holes (vias) and strip conductors (traces) on one side of the substrate using galvanic (electroplating) deposition of metal. The approach streamlines the creation of electrical connections between the front and back sides of the substrate while reducing process steps and eliminating the need for surface planarization on one side.

Use CasesContent extracted from patent full text and abstract with AI.

• Manufacturing of semiconductor biochips that require electrical contact from the top (sensor area) to the bottom for signal processing.
• Production of multi-layer printed circuit boards (PCBs) requiring efficient and reliable via and conductor formation.
• Creation of 3D integrated circuits (3D ICs) and chip stacks, where electrical interconnection through the substrate is necessary.
• Fabrication of high-density electronic packaging, such as multichip modules (MCMs), where precise and simultaneous via and trace creation improve integration.
• Mass production of advanced microfluidic chips in diagnostics and research, needing unobstructed top access and bottom-side electrical contacts.

BenefitsContent extracted from patent full text and abstract with AI.

• Enables simultaneous manufacturing of through-holes and conductors, saving processing time and resources.
• Reduces costs by minimizing the number of process steps compared to the traditional dual-damascene method.
• Eliminates or significantly reduces the need for time-consuming and potentially damaging surface planarization (polishing).
• Improves the accessibility of one side of the substrate (e.g., for microfluidics or sensors), enhancing design flexibility and functionality.
• Offers robust mechanical and electrical connections across the substrate, suitable for advanced electronic and bioelectronic devices.

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

The method involves covering an electrically insulated region of germination layers (13, 16) with a resist i.e. fixed resist. A boundary unit is arranged at a side of a substrate (11). A contact is provided from the germination layer (13) to a galvanization bath on the side of the substrate, and a metal is deposited on the layer (13), where the deposition of the metal is continued until the metal contacts the layer (16) arranged on another side of the substrate. A plated-through hole and a strip conductor are produced simultaneously on the latter side of the substrate by further deposition.