Memory Element, Stacking, Memory Matrix and Method for Operation

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This invention relates to a novel type of resistive memory element consisting of two serially-connected storage cells with high or low resistance states, which can be switched independently by electrical voltages. The design mitigates parasitic currents in memory arrays, allowing reliable scaling to very small feature sizes and supporting both memory and logic operations. The technology enables passive, high-density resistive memory matrices (such as RRAMs) that can also be used for in-memory logical computations, thus offering a compact, energy-efficient, and multifunctional approach to modern non-volatile memory and processing architectures.

Use CasesContent extracted from patent full text and abstract with AI.

• Non-volatile memory modules in computers and mobile devices (e.g., RRAM, next-generation flash memory)
• 3D high-density memory arrays for data centers and cloud storage solutions
• Embedded memory for Internet of Things (IoT) devices requiring low power and high endurance
• Logic-in-memory circuits or processing-in-memory architectures for AI accelerators or edge computing
• Massively parallel, energy-efficient hardware applied in neuromorphic (brain-inspired) computing systems
• Secure memory elements in cryptographic applications relying on physical unclonability

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly reduces parasitic/leakage currents in large-scale memory arrays, increasing reliability and data integrity
• Enables much higher memory density and smaller feature sizes (potentially below 10 nm), supporting miniaturization and higher capacity storage
• Low power consumption due to passive element design and low write/read voltages
• Improved endurance and lifespan as memory cells endure more write cycles at lower voltages
• Supports both binary storage and direct logic operation (processing-in-memory), breaking the traditional separation between memory and logic and helping mitigate the von Neumann bottleneck
• 3D stackable design maximizes silicon area use and enables highly integrated, large-scale memory architectures
• Material flexibility (using a variety of resistive switching materials) supports integration with hybrid and CMOS processes
• No need for embedded transistors in the memory matrix, minimizing area and thermal issues

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Inventors & Applicants

Patent Abstract

The invention relates to a memory element, to stacking, and to a memory matrix in which said memory element can be used, to a method for operating the memory matrix, and to a method for determining the truth value of a logic operation in an array composed of the memory elements. The memory element has at least one first stable state 0 and a second stable state 1. By applying a first write voltage V0, said memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the amount of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been developed, with which an array composed of the memory elements according to the invention can be turned into a gate for arbitrary logic operations.