Method of producing a tensioned layer on a substrate
Simple SummaryContent extracted from patent full text and abstract with AI.
This patent describes a method for creating strained (tensioned) silicon layers on a silicon-on-insulator (SOI) substrate. The process involves depositing specific layers on the substrate, introducing defect regions using ion implantation, and then relaxing certain layers through thermal treatments. This results in a strained silicon layer directly on the insulator, which improves the electrical properties of silicon-based devices without requiring complex wafer bonding or polishing steps.
Use CasesContent extracted from patent full text and abstract with AI.
- Manufacturing high-performance MOSFET and MODFET transistors for advanced CPU, GPU, or SoC chips.
- Production of fully depleted SOI (FD-SOI) transistors for low-power and high-speed electronic circuits.
- Fabrication of optoelectronic devices like photodetectors and quantum cascade lasers using strained silicon or SiGe layers.
- Creation of System-on-a-Chip (SoC) platforms that integrate varied strained and unstrained regions for different device types on a single wafer.
- Enabling flexible electronics by allowing strained films on flexible or glass substrates.
BenefitsContent extracted from patent full text and abstract with AI.
- Simplifies the fabrication of strained silicon layers by removing the need for wafer bonding or extensive polishing steps.
- Improves electron and hole mobility in transistors, leading to faster and more power-efficient semiconductor devices.
- Allows for selective and localized strain engineering, supporting advanced circuit design and integration.
- Compatible with existing industrial SOI wafer platforms (SIMOX, BESOI, etc.), supporting large-volume manufacturing.
- Achieves high crystal quality and low defect density, crucial for high-performance electronics and sensitive optoelectronics.
- Reduces overall process complexity and cost compared to conventional approaches.
- Enables construction of devices with both strained and unstrained regions in a planar, fabrication-friendly manner.
Technical Classifications (CPCs)
Main Classifications
Electrical & Electronic Tech
Sub Classifications
Electric Elements
Semiconductor & Solid-State Devices
CPC Codes
Inventors & Applicants
Inventors
Applicants
Forschungszentrum Juelich Gmbh
Patent Abstract
A silicon on insulator (SOI) substrate is converted into a strained SOI substrate by first providing an SOI substrate having a thin silicon layer and an insulator and at least one first epitaxial relaxing layer on the SOI-substrate. Then a defect region is produced in a layer by implantation of SI ions above the silicon layer of the SOI-substrate. Finally the first layer is relaxed by a thermal treatment in an inert atmosphere to simultaneously strain the silicon layer of the SOI-substrate via dislocation mediated strain transfer and to produce the strained silicon layer directly on the insulator.
Key Information
Publication No.
US7915148B2
Family ID
33304879
Publication Date
2011-03-29
Application No.
US49667609A
Application Date
2009-07-02
Priority Date
2009-07-02
Granted
Yes (3/10)
Possible Cooperation
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