Production of an Ohmic Contact and Electronic Component with Ohmic Contact

Publication: DE102019205376A1
Published: 2020-10-15
Family Size: 10
Granted: Yes (4/10)

Simple SummaryContent extracted from patent full text and abstract with AI.

This invention describes a method for producing low-resistance (ohmic) electrical contacts to semiconductor layers in electronic devices, especially those with buried II-VI or III-V compound semiconductors, which are sensitive to high temperatures and surface damage. The process involves wet-chemical etching of the semiconductor surface, radical cleaning (preferably with hydrogen radicals), and subsequent application of a semiconductor or metallic conductor. The approach allows excellent local ohmic contacts without damaging the crystal structure and enables their use at both room and low temperatures, ideal for advanced electronic and quantum devices.

Use CasesContent extracted from patent full text and abstract with AI.

  • Fabrication of high-performance field-effect transistors (FETs) using II-VI or III-V semiconductors.
  • Development of electronic spin qubit devices for quantum computing requiring low-resistance, low-temperature contacts.
  • Manufacture of high-mobility electronic devices for advanced microelectronics.
  • Integration of unipolar devices with robust, reliable local contacts even on temperature-sensitive semiconductor materials.
  • Production of multi-layered semiconductor structures for sensors or optoelectronics where traditional contact methods are unsuitable.

BenefitsContent extracted from patent full text and abstract with AI.

  • Enables reliable ohmic contacts to buried, temperature-sensitive semiconductors where other techniques fail.
  • Maintains crystal integrity and high conductivity by avoiding high-temperature processes and surface damage.
  • Delivers extremely low contact resistance, critical for both standard and low-temperature electronics.
  • Supports creation of devices suitable for quantum technology (e.g., electron spin qubits) and advanced transistors.
  • Compatible with selective area development (regrowth), simplifying device architecture and allowing for precise local contacts.

Technical Classifications (CPCs)

Main Classifications

Electrical & Electronic Tech

Sub Classifications

Electric Elements

Semiconductor & Solid-State Devices

CPC Codes

H01L21/02477H01L21/02557H01L21/0256H01L21/02568H01L21/02642H01L21/28575H01L21/443H10D62/82

Inventors & Applicants

Applicants

Forschungszentrum Juelich

Patent Abstract

The invention relates to a method for producing an ohmic contact for an electronic component. A layer (3) consisting of a semiconductor is directly or indirectly applied onto a substrate (1). The invention is characterized in that a surface to be contacted of the applied semiconductor (3) is wet-chemically etched. The wet-chemically etched surface is then rinsed with radicals, and an electric conductor (8) or a semiconductor (7) is applied onto the surface rinsed with radicals. The invention additionally relates to an electronic component comprising multiple semiconductor layers (2, 3, 4) on a substrate (1), a cover layer (5) on the one or more semiconductor layers (2, 3, 4) applied onto the substrate (1), said cover layer (5) consisting of an electrically non-conductive dielectricum, and an entrance (6) which leads through the cover layer to a semiconductor layer (3), wherein adjacent semiconductor layers (2, 3, 4) consist of different II-VI semiconductors, and the entrance (6) is at least partly filled with a II-VI semiconductor (7). A metal contact (8) is applied onto the II-VI semiconductor (7), said metal contact reaching the exterior of the cover layer (5) or protruding outwards beyond the cover layer (5).

Key Information

Publication No.

DE102019205376A1

Family ID

70228022

Publication Date

2020-10-15

Application No.

DE102019205376A

Application Date

2019-04-15

Priority Date

2019-04-15

Granted

Yes (4/10)

Possible Cooperation

For further information please contact the transfer office.