Tunnel Field-Effect Transistor and Method for Its Manufacture

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This invention relates to a new design and manufacturing process for tunnel field-effect transistors (TFETs). By using a combination of selective silicidation and targeted dopant segregation in the source region, the TFET achieves a steeper tunnel edge, a shortened tunnel barrier, and an enlarged tunnel contact area. The tunnel junction is aligned parallel to the electric field of the gate, and is created in a material with a smaller band gap (such as SiGe). The process allows for highly precise, reproducible creation of the tunnel junction, improving the transistor’s energy efficiency and performance compared to prior approaches.

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• Ultra-low power logic circuits for mobile devices and wearable electronics
• High-density integrated circuits (ICs) for advanced computing hardware
• Energy-efficient processors for laptops and data centers
• Nanoelectronics and multigate transistors in cutting-edge semiconductor technology
• Replacement or supplementation of conventional MOSFETs in future CMOS technology nodes

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly reduced power consumption due to steep subthreshold slope (<60 mV/dec)
• Higher energy efficiency, enabling lower operating voltages without performance loss
• Increased tunnel current and improved on/off ratio for robust digital switching
• Precise, reproducible manufacturing with fewer defects, thanks to self-aligned silicidation and dopant segregation
• Compatibility with advanced materials (e.g., SiGe, GeSn), allowing further scaling of transistor dimensions
• Applicable to both planar and nanowire/multigate device architectures, expanding integration possibilities

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Patent Abstract

The invention relates to a tunnel field-effect transistor (TFET) having, in particular, two advantages over the prior art. First, a shortened tunnel barrier and thus a shortened tunnel junction are provided. This is effected in that silicidation and additionally dopant segregation are provided in the source region, which bring about a steeper tunnel edge. Second, the tunnel surface itself is enlarged by means of selective and self-adjusting silicidation, wherein, in the case of the tunnel field-effect transistor (TFET) according to the invention, a tunnel junction that extends parallel to the electric field lines of the gate is provided. The tunnel field-effect transistor (TFET) according to the invention thus combines a tunnel junction parallel to the electric field lines of the gate and having an enlarged tunnel region below the gate with a material that has a narrower band gap. The method according to the invention for producing the TFET comprises selective, self-adjusting silicidation and additionally dopant segregation. These steps make it possible to produce the tunnel junction reproducibly with an accuracy of a few nanometers.