Multi-Stage Analog-to-Digital Converter
Simple SummaryContent extracted from patent full text and abstract with AI.
This invention describes a multi-stage analog-to-digital converter (ADC) system for electronic devices, enabling high-speed digitization of analog signals. By using two separate memory units to store alternating analog signals and multiple ADCs operating in parallel or sequentially, the system achieves higher sampling rates and improved signal resolution. It employs a combination of sample-and-hold circuits, flash ADCs, and successive approximation (SAR) ADCs, enabling fast and accurate conversion of analog signals to digital form with hardware-efficient architecture.
Use CasesContent extracted from patent full text and abstract with AI.
- High-speed data acquisition systems in scientific instruments
- Digital oscilloscopes and spectrum analyzers requiring fast, high-resolution sampling
- Medical imaging devices like MRI and EEG that demand rapid, accurate analog-digital conversion
- Communication systems (e.g., 5G/6G base stations) needing efficient high-frequency signal digitization
- High-resolution audio recording and processing equipment
- Industrial monitoring equipment, such as high-speed sensors and controls
BenefitsContent extracted from patent full text and abstract with AI.
- Significantly increased sampling rates due to parallelization and efficient sample management
- Improved resolution and accuracy in the digitization process, even with low-resolution individual ADC stages
- Reduced hardware complexity compared to implementing a single high-resolution and high-speed ADC
- Efficient use of memory and sampling components for continuous, high-throughput conversion
- Scalable design allows for adaptation to various application requirements (resolution, speed, cost)
- Mitigation of signal losses and noise by using sample-and-hold techniques and multi-stage processing
Technical Classifications (CPCs)
Main Classifications
Electrical & Electronic Tech
Sub Classifications
Electronic Circuitry
CPC Codes
Inventors & Applicants
Applicants
Forschungszentrum Juelich Gmbh
Patent Abstract
The invention relates to an electronic device having a first memory (1, 7) for storing an analogue signal and a second memory (2, 8) for storing another analogue signal, and having an ADC that can digitize the one and the other analogue signal in alternating fashion. The invention furthermore relates to a method for digitizing an input signal by way of an electronic device, wherein a first input signal is digitized by a first ADC of the electronic device and at the same time a second input signal is digitized by a second ADC of the electronic device. The invention enables a high sampling rate.
Key Information
Publication No.
DE102023205734A1
Family ID
90572138
Publication Date
2024-12-24
Application No.
DE102023205734A
Application Date
2023-06-20
Priority Date
2023-06-20
Granted
No
Possible Cooperation
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