Memory element i.e. bipolar switching memory element, for resistive RAM, has memory cell connected in series with another memory cell, where each cell exhibits two stable states with respective high and low electrical resistances

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This patent describes a resistive RAM (ReRAM) memory element design where two memory cells are connected in series, and each cell can switch between high and low resistance states. The element is able to achieve different resistance values depending on the applied voltage, which enables different logical operations and improved memory storage techniques.

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• Non-volatile memory devices for computers and servers
• Embedded memory for Internet of Things (IoT) devices
• High-density memory arrays for mobile devices
• Data storage in artificial intelligence and machine learning hardware
• Advanced logic circuits using memory elements with resistive switching
• Reconfigurable computing architectures

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• Enables high-density memory storage due to compact cell design
• Supports non-volatile data retention, meaning data is kept even after power is removed
• Can reduce power consumption by utilizing different resistance states for operations
• Improves reliability and stability of memory elements through bipolar switching
• Allows implementation of advanced logic functions within memory arrays
• Potentially faster read/write operations compared to traditional memory technologies

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Patent Abstract

The element has a memory cell (A) connected in series with another memory cell, where each cell exhibits one stable state with high electrical resistance and another stable state with low electrical resistance. The element is transferable into a high-impedance state by applying write voltage in the former stable state and into another high-impedance state by applying another write voltage in the latter stable state. The memory element exhibits different electrical resistance values by applying read voltage, where amount of read voltage is smaller than the write voltages. Independent claims are also included for the following: (1) a method for operating a memory element, a stack of memory elements or a memory matrix (2) a method for determining a logical value of logic interconnection of two variables in an array of memory elements.