Field Effect Transistor for Generating Tunnel Currents with Vertical Current Path Through Thin Layers

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This patent describes a special type of field-effect transistor (FET) that can generate tunnel currents using a vertical current path through thin layers. It features a unique arrangement of doped and semiconductor layers on an insulating substrate, with source, gate, and drain electrodes positioned in a specific, horizontally offset manner to optimize tunneling effects.

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• Development of high-speed, low-power electronic switches for integrated circuits
• Production of advanced logic gates and memory devices
• Implementation in nanoscale semiconductor devices where tunneling effects can be utilized
• Use in quantum computing or sensing applications requiring precise control of tunnel currents

BenefitsContent extracted from patent full text and abstract with AI.

• Improved control over tunneling currents, allowing for more efficient electronic devices
• Potential for smaller device sizes due to vertical current paths and thin-layer design
• Reduced power consumption and enhanced switching speeds compared to traditional transistors
• Enables new architectures in semiconductor device manufacturing

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Patent Abstract

The invention relates to a field effect transistor for generating tunnel currents with a vertical current path through thin layers. This comprises a gate arranged along a common connection line between source and drain. It is characterized in that a doped first layer is arranged on an electrically insulating substrate and an electrically semiconducting second layer is arranged on this first layer. In each case, a partial area of the upper side surface of one layer is arranged horizontally offset relative to the upper side surface of the other layer. Source is arranged on the first layer at a distance beside the second layer. Gate is arranged on the second layer. In this case, at least a partial area of the gate electrode is arranged without horizontal offset relative to the upper side surface of the first layer. Drain is arranged on the second layer completely horizontally offset relative to the upper side surface of the first layer.