Method for the Follow-On Processing of a Silicon Layer with a Structure Created by Liquid-Phase Crystallization

Publication: WO2016015714A1
Published: 2016-02-04
Family Size: 3
Granted: Yes (1/3)

Simple SummaryContent extracted from patent full text and abstract with AI.

This invention presents a method for post-processing thin silicon layers that have been structured using liquid-phase crystallization (LPC-Si), which is primarily intended for thin-film solar cell applications. The method relies exclusively on sequential plasma-chemical processes carried out in one (or optionally two) vacuum process chambers, thus avoiding time-consuming and resource-intensive alternation with wet-chemical methods. Through plasma etching, unwanted oxide and defective material are removed; hydrogen plasma is then used for defect passivation. Optionally, a protective covering layer can be deposited, and further steps such as texturing or emitter/buffer layer additions can be integrated, all without breaking vacuum or moving the substrate between multiple systems.

Use CasesContent extracted from patent full text and abstract with AI.

  • Manufacturing high-efficiency thin-film silicon solar cells using liquid-phase crystallized silicon.
  • Mass production of silicon absorber structures for photovoltaic modules on large low-cost glass substrates.
  • Integrated, in-line processing lines for thin-film electronics where plasma-only processes are preferable over mixed wet/dry approaches.
  • Production of solar cells and modules with improved material quality and lower production costs.
  • R&D of next-generation photovoltaic devices seeking to eliminate or simplify vacuum-to-air transfer processes.

BenefitsContent extracted from patent full text and abstract with AI.

  • Reduces equipment and material costs by eliminating the need for wet-chemical processing steps and additional chambers.
  • Increases throughput and production speed by enabling all steps to occur in direct sequence without interrupting the vacuum, thus minimizing substrate handling and transfer times.
  • Enhances the quality and efficiency of the thin silicon absorber layers by more effectively removing defects and passivating the material within a controlled plasma environment.
  • Facilitates scalable production using existing industrial plasma-enhanced chemical vapor deposition (PECVD) chambers, making it suitable for large-area substrates.
  • Minimizes use of hazardous chemicals such as acids and bases as required in wet processing, improving workplace safety and environmental impact.
  • Improves reproducibility and consistency of the final product due to integration and automation of all process steps within a single or limited set of process chambers.

Technical Classifications (CPCs)

Main Classifications

Electrical & Electronic Tech

Sub Classifications

Semiconductor & Solid-State Devices

CPC Codes

H10F71/129H10F71/131

Inventors & Applicants

Applicants

Helmholtz Zentrum Berlin für Materialien und En Gmbh

Patent Abstract

For solid-phase-crystallized silicon (SPC-Si) in a thin layer there are existing procedures that alternate between wet-chemical processes under atmospheric pressure and plasma-chemical processes in a vacuum. A known method uses successive plasma-enhanced method steps for the deposition, cleaning and texturing of a silicon wafer. In the case of the method according to the invention, exclusively plasma-chemical method steps are carried out in a direct sequence without interruption of the vacuum, whereby the quality of the thin silicon absorber layer (01) of liquid-phase-crystallized silicon (LPC-Si) is increased and the processing costs are lowered. Quality-reducing surface oxide (05) and defect-rich material (09) are removed by plasma-chemical etching and a defect passivation is performed by means of a hydrogen plasma. At the end of the defect passivation, a protective covering layer may be optionally deposited. The method can be carried out in one process chamber or, if a covering layer is formed, in two process chambers. The method may be concluded by the directly following deposition of an intrinsic buffer layer and/or a counterdoped emitter layer.

Key Information

Publication No.

WO2016015714A1

Family ID

54065145

Publication Date

2016-02-04

Application No.

DE2015100311W

Application Date

2015-07-22

Priority Date

2014-07-28

Granted

Yes (1/3)

Possible Cooperation

For further information please contact the transfer office.