Method for Producing Unilaterally Arranged Structured Contacts in a Layer Arrangement for a Photovoltaic Device

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This invention discloses an improved method for making structured electrical contacts on one side of a multilayer arrangement in photovoltaic components, such as solar cells. The process involves the use of doped, silicon-rich layers as the main semiconductor materials, along with one or two masking layers engineered for selective etching. The etching sequence is optimized for high process speed and reliability, utilizing strategic roughening and a lift-off process to quickly and precisely expose contact areas, reducing complexity and time compared to existing techniques.

Use CasesContent extracted from patent full text and abstract with AI.

• Manufacturing high-efficiency crystalline silicon or heterojunction (a-Si/c-Si) solar cells with rear-side contacts
• Production of advanced photovoltaic modules requiring fine, structured contacts with precise alignment
• Industrial-scale fabrication processes for solar cells optimizing throughput and minimizing manufacturing costs
• Adaptation to other semiconductor device manufacturing where structured, doped contacts are needed

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly speeds up the contact patterning and lift-off process, making manufacturing faster and more efficient
• Eliminates the need for sophisticated photolithography or costly alignment steps, lowering production costs
• Reduces risk of substrate damage and potential short circuits by enabling selective, gentle etching and self-aligned structures
• Allows full surface passivation and electrical isolation between contact regions, improving device performance and longevity
• Compatible with standard industrial deposition methods (like PECVD) and avoids the use of organic photoresists
• Adaptable to different device architectures and both front- and rear-contact solar cell designs

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Patent Abstract

The invention relates to a method, wherein a doped silicon-rich layer that is nanocrystalline or amorphous is used as a first doped semiconductor layer of a first conductivity type and/or as a second doped semiconductor layer having the opposite conductivity type. Two masking layers having materials of different selective etchability are applied for the masking layer arrangement, wherein the masking layer arranged closest to the substrate is a silicon-poor layer having greater etchability in HF-containing etchant than the second masking layer, which is silicon-rich and can be etched in Si-etching etchant. The etching of the structured masking layer arrangement is performed in a silicon-etching solution in at least one etching step at least in order to remove the first doped silicon-rich layer in the contact openings and in order to remove the Si-rich masking layer in the unstructured regions of the masking layer arrangement, wherein at the same time the remaining exposed surface of the Si-poor masking layer is roughened, and the at least partial removal of the still remaining silicon-poor masking layer and of the second doped silicon-rich layer arranged on the rough surface of said silicon-poor masking layer is performed by means of a lift-off process in an HF-containing solution in order to expose the structured first silicon-rich layer. The same result is achieved by using only one masking layer having a silicon gradient.