Manufacturing defectless crystalline silicon layer on substrate by chemical or physical gas phase deposition, comprises supplying less amount of nitrogen during the coating of the substrate, and supplying other element as dopant material

Publication: DE102009056162A1
Published: 2011-09-15
Family Size: 2
Granted: Yes (1/2)

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent describes a method for producing a defect-free crystalline silicon layer on various substrates (such as silicon wafers or amorphous substrates) through chemical or physical gas phase deposition. By deliberately using very little nitrogen during the process or keeping the substrate at low temperatures, the formation of unwanted silicon nitride is minimized. Additionally, a dopant element is introduced to adjust the electrical conductivity of the silicon layer.

Use CasesContent extracted from patent full text and abstract with AI.

  • Manufacturing high-quality silicon wafers for solar panels
  • Producing defect-free semiconductor layers for integrated circuits and electronic devices
  • Creating advanced silicon-based sensors with precise electrical properties
  • Fabricating crystalline silicon layers for use in thin-film transistors and display technology
  • Developing next-generation power devices or microchips with improved reliability

BenefitsContent extracted from patent full text and abstract with AI.

  • Reduces defects in crystalline silicon layers, leading to higher device performance
  • Improves control over electrical properties by allowing precise doping during deposition
  • Minimizes unwanted nitride formation, which can otherwise degrade material quality
  • Enables use of different substrate types, increasing versatility in device production
  • Enhances scalability and potential cost-effectiveness of producing high-quality silicon layers

Technical Classifications (CPCs)

Main Classifications

Chemistry & Materials Science

Electrical & Electronic Tech

Sub Classifications

Crystal Growth

Electric Elements

Semiconductor & Solid-State Devices

CPC Codes

C30B23/02C30B25/02C30B29/06H01L21/02381H01L21/02532H01L21/02573H01L21/02579H01L21/02631H10F10/16H10F71/1224H10F71/131H10F71/1395H10F77/122

Inventors & Applicants

Applicants

Helmholtz Zent B Mat & Energ

Patent Abstract

Manufacturing a defectless crystalline silicon layer on a substrate by chemical or physical gas phase deposition, comprises supplying less amount of nitrogen during the coating of the substrate with silicon so that strong substoichiometric ratio of nitrogen to deposited silicon is maintained or maintaining the substrate temperature at low level so that the energetic reaction conditions for nitride formation is not attained, and supplying a further element as dopant material during the coating process, for altering the conductivity of the defectless crystalline silicon layer. Manufacturing a defectless crystalline silicon layer on a substrate by chemical or physical gas phase deposition, comprises supplying less amount of nitrogen during the coating of the substrate with silicon so that strong substoichiometric ratio of nitrogen to deposited silicon is maintained or maintaining the substrate temperature at low level so that the energetic reaction conditions for nitride formation is not attained, and supplying a further element as dopant material during the coating process, for altering the conductivity of the defectless crystalline silicon layer. The nitrogen is added in an amount such that it is present in the silicon-layer in a concentration in a ppb- to ppm-range. A crystalline substrate is used. A silicon-wafer is used as the crystalline substrate. A carrier provided with a polycrystalline seed layer is used as the crystalline substrate. An amorphous substrate is used and the silicon-layer separated on the amorphous substrate is recrystallized by energy supply. The less amount of the nitrogen to be supplied from the pure nitrogen involved on the coating process is placed to the disposal.

Key Information

Publication No.

DE102009056162A1

Family ID

44507639

Publication Date

2011-09-15

Application No.

DE102009056162A

Application Date

2009-11-27

Priority Date

2009-11-27

Granted

Yes (1/2)

Possible Cooperation

For further information please contact the transfer office.