Fast readout method and swiched capacitor array circuitry for waveform digitizing

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This patent introduces a fast readout method and specialized switched capacitor array (SCA) circuitry for high-precision waveform digitizing. The invention provides an efficient way to sample and store analog signals across multiple channels at very high speeds and allows selective, rapid readout of specific parts (regions of interest) of the acquired waveform. This significantly reduces data readout time and system dead-time, making it ideal for applications demanding high channel density, low latency, and high analog bandwidth. The chip is built for stability, low noise, and radiation tolerance, making it suitable for demanding environments.

Use CasesContent extracted from patent full text and abstract with AI.

• Waveform digitizing in high-energy physics experiments (e.g., particle detectors, photomultiplier readout)
• Fast readout of signals in medical imaging equipment (such as PET and CT scanners)
• Analog signal monitoring in synchrotron or fusion research facilities
• High-speed transient recording and signal analysis in scientific instrumentation
• Any system requiring fast and precise analog-to-digital conversion of multi-channel waveforms, such as oscilloscopes or high-speed test equipment

BenefitsContent extracted from patent full text and abstract with AI.

• Reduces waveform readout time by enabling partial (region of interest) readout, lowering overall system dead-time
• Supports very high sampling speeds (from 10 MSPS up to 5 GSPS) and high channel density (12 channels per chip)
• Delivers high analog bandwidth (450 MHz) and very low noise (0.35 mV after calibration)
• Highly precise timing (timing resolution <100 ps achievable with calibration and proper configuration)
• Low power consumption and multiplexed or parallel readout flexibility
• Radiation-hardened design allows use in harsh environments such as physics experiments or space
• Improved scalability and cost-effectiveness for systems requiring multiple simultaneous high-speed waveform digitizations

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Inventors & Applicants

Patent Abstract

The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling cells is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).