A single photon counting readout chip with neglibible dead time

Simple SummaryContent extracted from patent full text and abstract with AI.

This invention describes a single photon counting pixel detector chip with near-zero dead time, enabling extremely high frame rates. The chip uses a unique architecture with a temporary capacitor buffer, highly parallelized readout, and advanced crosstalk suppression techniques. It allows images to be continuously captured and read out, with selectable counter depth for tradeoffs in speed and dynamic range.

Use CasesContent extracted from patent full text and abstract with AI.

• X-ray imaging in synchrotron experiments (e.g., materials science, crystallography)
• Medical X-ray imaging requiring high frame rates and resolution
• Non-destructive testing using fast, high-resolution detectors
• Laboratory diffractometers for rapid data acquisition
• Time-resolved pump-probe experiments with simultaneous multi-frame capture in variable conditions

BenefitsContent extracted from patent full text and abstract with AI.

• Negligible dead time allows virtually continuous imaging and maximum detector utilization
• Extremely high frame rates improve time resolution and throughput
• Selectable counter depth offers flexible tradeoff between dynamic range and speed
• Parallelized readout architecture minimizes readout bottlenecks and improves scalability
• Advanced techniques significantly reduce digital-to-analog crosstalk, maintaining signal integrity even at small pixel sizes
• Enables smaller pixel sizes, increasing spatial resolution
• Robustness against cross-interference makes design suitable for sensitive analog applications
• High testability and flexible operation modes ease integration into advanced experimental setups

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Patent Abstract

It is an objective of the present invention to provide a single photon counting pixel detector chip having a negligible dead time and consequentially high frame rates. This objective is achieved by a single photon counting pixel detector chip, comprising: a) a layer of photosensitive material; b) an N x M array of photo-detector diodes arranged in said layer of photosensitive material; each of said photo-detector diodes having a diode output interface; c) a N x M array of readout unit cells, one readout unit cell for each photo-detector diode; d) said readout unit cell comprising: d1) an input interface connected to said diode output interface, a high-gain charge to voltage amplifying means and a pixel counter being connected to an output of the high-gain voltage amplifying means, d2) said pixel counter being split into a first number of nibble counters, each nibble counter having an individual number of bits, wherein for each bit a basic counter cell is provided; said basic counter cell comprising a counting element, a switch, a temporary storage element and an output stage, wherein said basic counter cells are cascaded; e) a side shift register to read out the nibble counters row-wise with a predetermined number of nibble row selections wherein the data stored in the temporary storage elements on the selected nibble counter row are sent on a parallel bus as currents and are transformed in digital levels by parallel bus receivers.