Methods of Manufacturing Semiconductor Devices

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This invention presents a new method for manufacturing silicon carbide (SiC)-based semiconductor devices, such as power transistors and sensors, with improved performance and lower cost. The method involves layering differently-doped SiC materials on a SiC substrate and creating precise patterns of pits (vias) through the substrate using electrochemical etching. The special arrangement and doping of layers allow specific regions to be selectively removed or stopped during etching, which helps decrease resistance and enables new device structures, such as low-resistance contacts, enhanced sensors, and freestanding graphene membranes.

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• Fabrication of SiC power electronic devices (e.g., Schottky diodes, MOSFETs, IGBTs) with reduced on-state resistance for efficient power conversion.
• Manufacturing of GaN-based high electron mobility transistors (HEMTs) for telecommunications and RF applications.
• Production of advanced sensors based on SiC with enhanced optical properties, such as quantum sensors using spin-active point defects.
• Creation of freestanding graphene membranes on SiC substrates for use in ultrafast transistors, gas sensors, or optical sensors.
• Device structures that require through-wafer vias or patterns for improved electrical or thermal management in microelectronics.

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• Reduces the specific on-resistance (RON) of power semiconductor devices, improving energy efficiency and lowering heat generation.
• Lowers manufacturing costs by allowing for high throughput, selective etching, and less need for expensive wafer thinning or transfer processes.
• Enables more complex and high-performance device architectures, such as integration of graphene membranes or quantum sensing elements on SiC.
• Improves the quality of epitaxial layers through optimized buffer and etch-stop layering, enhancing device reliability and performance.
• Allows for monolithic integration and new applications by facilitating wafer-scale processing and through-substrate patterning.

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Patent Abstract

It is therefore the objective of the present invention to provide a method for the generation of electronic devices that have excellent electronic behavior at low manufacturing cost.This objective is achieved according to the present invention by a method of forming at least a part of a power semiconductor device, the method comprising the steps of:a) homoepitaxially forming at least two silicon carbide layers (101, 102) on a first side of a silicon carbide substrate (100);b) forming a pattern of pits (110) on a second side of the silicon carbide substrate (100);c) wherein the at least two layers comprising a first layer, hereinafter referred to as buffer layer (101), on the first side of the silicon carbide substrate (100) having the same doping type of the silicon carbide substrate (100) and a doping concentration equal or greater than 1017 cm-3 in order to increase the quality of at least one subsequent SiC layer; andd) wherein the at least two layers comprising a second layer, hereinafter referred to as etch stopper layer (102), being deposited on the buffer layer (101) and having the same doping type of buffer layer (101) but a lower doping concentration in order to block a trenching process; ande) wherein the pattern of pits (110), obtained by electrochemical etching, extends completely thorough at least the silicon carbide substrate (100) and the buffer layer (101).Thus, the embodiments of the present invention provide improvements to state of the art power semiconductor device by providing designs that employ a set of Silicon Carbide doped epitaxies to selectively dissolve regions of the SiC substrate, i.e. generate a pattern of vias or pits, to improve the performances, e.g. reduce the specific on-resistance, of the semiconductor based devices.