A Semiconductor Device Featuring an Arched Structure Strained Semiconductor Layer

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This patent describes a semiconductor device, such as a transistor, that utilizes a mechanically strained semiconductor channel with an arched or non-linear geometry. The strained channel is formed over a point location on a dielectric layer using specially engineered seed and stress-inducing layers (often involving materials like Ge, SiGe, or Si) to create a single-crystalline arch-shaped structure. This configuration enhances the performance of field-effect transistors (FETs) by tuning strain more easily and allowing new device architectures such as surround-gate or double-gate transistors. The method also enables integration in advanced CMOS fabrication and 3D integrated circuits.

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• High-performance CMOS logic circuits requiring greater drive current and enhanced speed.
• Low-power CMOS devices for mobile and energy-sensitive applications.
• Advanced transistor structures including surround-gate or double-gate MOSFETs for scaling beyond current limits.
• 3D integrated circuit fabrication where layers of different devices are stacked.
• Potential application in optoelectronic devices like diodes, LEDs, or lasers due to the strained semiconductor layer.
• Manufacturing of integrated circuits with mixed device types (digital, analog, and optical) on the same chip.

BenefitsContent extracted from patent full text and abstract with AI.

• Improved transistor performance through enhanced channel strain, resulting in higher drive currents and faster switching speeds.
• Greater control and tunability of the strain level within devices, allowing for performance optimization across a wafer.
• Simplified manufacturing compared to traditional strained silicon methods (e.g., no need for thick buffer layers or wafer bonding).
• Compatibility with both high-performance and low-power applications, enabling versatility in IC design.
• Potential for fully depleted operation due to thin, high-quality strained channels, translating to lower leakage and better control.
• Enabled advanced device architectures with surround or dual-gates for superior electrostatic control and further scaling.
• Smooth, epitaxially defined interfaces, avoiding roughness from conventional etching processes.

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Patent Abstract

A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. Ih addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.