Method for increasing non-volatile NAND flash memory holding time during operation of charge-trapping based non-volatile semiconductor memory cells, involves adjusting pulses such that pulses reduce voltage approximately to target voltage

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This patent describes a method to improve the data retention time (holding time) of NAND flash memory by carefully controlling programming pulses during the operation of charge-trapping, non-volatile semiconductor memory cells. By adjusting these voltage pulses to approach a desired target voltage, the method enables more precise programming and prolongs the time data can be reliably stored in the memory cells.

Use CasesContent extracted from patent full text and abstract with AI.

• Enhanced reliability and lifespan of NAND flash memory in solid-state drives (SSDs)
• Data storage in portable electronic devices such as smartphones, tablets, and cameras
• Enterprise storage solutions requiring long-term data integrity
• Embedded systems with critical data retention needs, such as automotive and industrial control systems
• Medical devices which rely on non-volatile memory for patient data retention

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly increases the data retention time of NAND flash memory
• Improves overall reliability and performance of memory storage devices
• Reduces the risk of data loss or corruption in electronic devices
• Extends the functional lifespan of flash memory chips
• Enables applications requiring high data integrity and long-term storage

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Inventors & Applicants

Patent Abstract

The method involves adjusting charge-trapping based non-volatile semiconductor memory cells for implementing a storing process with programming pulses (9) of polarity on cut-off voltage. Voltage pulses are supplied to the memory cells. The cut-off voltage is selected such that the voltage lies above desired target cut-off voltage for the memory cells. The voltage pulses connected to verification pulses (10) are adjusted such that the voltage pulses reduce the cut-off voltage of the memory cells approximately to the target cut-off voltage. An independent claim is also included for a device for operating charge-trapping based-non volatile semiconductor memory cells.