Layer Assembly

Publication: WO2012130676A2
Published: 2012-10-04
Family Size: 8
Granted: Yes (3/8)

Simple SummaryContent extracted from patent full text and abstract with AI.

This invention describes a method for fabricating precise arrangements of nanostructures (such as quantum dots or photon emitters) on a layered semiconductor assembly. Instead of using complex and potentially damaging nanolithography, the method locally modifies a buried layer to create mechanical strain in an upper layer. This strain precisely dictates where nanostructures form when a strain-sensitive material is deposited—enabling defect-free and deterministic placement of nanostructures on the surface.

Use CasesContent extracted from patent full text and abstract with AI.

  • Manufacture of highly efficient single photon sources for quantum communication and computing.
  • Development of advanced optoelectronic devices such as lasers, LEDs, and quantum dot devices.
  • Fabrication of nano-scale sensors or detector arrays with controlled positioning.
  • Enabling defect-free nanostructures for photonic circuits and on-chip quantum technologies.
  • Production of precisely located nanostructures for research and development in nanotechnology.

BenefitsContent extracted from patent full text and abstract with AI.

  • Allows deterministic and highly precise placement of nanostructures without complex, damage-prone lithography.
  • Enables fabrication of nanostructures on unstructured, defect-free surfaces, leading to higher device performance.
  • Improves current injection efficiency and device alignment through self-aligned apertures and strain-guided growth.
  • Reduces manufacturing complexity and cost by eliminating the need for nanoscale pre-patterning.
  • Provides versatility in device design by allowing different shapes and arrangements through strain engineering.

Technical Classifications (CPCs)

Main Classifications

Electrical & Electronic Tech

Manufacturing & Transport

Sub Classifications

Electric Elements

Nanotechnology

Semiconductor & Solid-State Devices

CPC Codes

B82Y20/00H01S5/3412H10D62/00H10H20/811

Inventors & Applicants

Applicants

Univ Berlin Tech

Strittmatter Andre

Schliwa Andrei

Germann Tim David

Pohl Udo W

Gaysler Vladimir

Schulze Jan-hindrik

Patent Abstract

The invention inter alia relates to a method of fabricating a layer assembly comprising the steps of: arranging a first layer on top of a carrier; arranging a second layer on top of the first layer; locally modifying the material of the buried first layer and providing at least one modified section in the first layer, wherein the modified material changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section; after locally modifying the material of the buried first layer, depositing a third material on top of the second layer, at least one characteristic of the third material being sensitive to the local mechanical strain in the second layer.

Key Information

Publication No.

WO2012130676A2

Family ID

45954618

Publication Date

2012-10-04

Application No.

EP2012054948W

Application Date

2012-03-21

Priority Date

2011-03-30

Granted

Yes (3/8)

Possible Cooperation

For further information please contact the transfer office.