Hardness Amplification of Physical Unclonable Functions (pufs)

Simple SummaryContent extracted from patent full text and abstract with AI.

This invention describes a method for improving the security (hardness) of physical unclonable functions (PUFs) by combining multiple PUFs with logic gates to create a stronger, more tamper-resistant hardware security primitive. The system enrolls and authenticates devices based on unique responses generated by these combined PUFs, making each physical device difficult to clone or counterfeit.

Use CasesContent extracted from patent full text and abstract with AI.

• Device authentication for IoT devices and smart cards
• Secure identity verification in access control systems
• Protection against hardware counterfeiting and tampering
• Generation of secure cryptographic keys bound to physical devices
• Supply chain security for verifying origin of microelectronics

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly increases security compared to single PUFs by making cloning and modeling attacks more difficult
• Enables reliable and unique device authentication with minimal added hardware complexity
• Enhances resistance to hardware-based attacks and tampering
• Provides a low-cost and scalable solution for hardware security applications
• Does not require external secure memory as secrets are derived from the physical characteristics of the device itself

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.