Memory Cell, and Method for Storing Data

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This patent describes a new type of semiconductor memory cell and a method for storing data within it. The core idea is to use a semiconductor heterostructure with a variable potential well for trapping or releasing charge carriers, thereby representing binary information. The relative spatial arrangement of the heterostructure and a space charge region is dynamically controlled by applying different voltages for writing, erasing, and retaining data. The design allows for both very fast write/read times and long data retention, potentially outperforming DRAM and Flash memory.

Use CasesContent extracted from patent full text and abstract with AI.

• Next-generation non-volatile memory for computers and servers
• High-density storage solutions for mobile devices (phones, tablets, handheld gadgets)
• Embedded memory in IoT devices and smart sensors
• Data storage in digital cameras, wearables, and portable electronics
• Memory for mission-critical applications where endurance and retention are key (e.g., automotive, aerospace, industrial controls)
• Multi-level cell memories for data centers and cloud computing

BenefitsContent extracted from patent full text and abstract with AI.

• Faster write and erase operations compared to traditional Flash memory
• Significantly longer data retention compared to DRAM
• Lower power consumption due to potential for smaller charge manipulation and efficient operation
• High endurance with more possible write/erase cycles
• Scalable to high-density memory via nanostructures and multi-level cell capability
• Potential to store more information using fewer carriers, improving efficiency and miniaturization
• Flexible material system suitable for modern semiconductor fabrication processes

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure. The semiconductor heterostructure and the space charge region are spatially arranged relative to one another in such a way that the semiconductor heterostructure is located within the space charge region when the maintaining voltage is applied, at the edge of or outside the space charge region when the supply voltage is applied, and within the space charge region when the discharge voltage is applied.