A Computer Processor

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This patent covers a computer processor architecture based on a spatial array of processing elements (PEs), where each PE can independently store, decode, and execute instructions. The architecture uses a specialized data bus for both data and instruction distribution across the array, enabling decentralized execution and efficient data exchange. The system allows the processor to dynamically allocate resources, minimize instruction fetching, and efficiently run general-purpose code with high reusability of instructions, leading to reduced energy consumption and increased performance, particularly in parallel and multithreaded scenarios.

Use CasesContent extracted from patent full text and abstract with AI.

• General-purpose computing for low-power devices (e.g., IoT, mobile processors)
• High-performance embedded systems requiring efficient parallelism
• Edge computing where energy efficiency is critical
• Machine learning inference and dataflow-heavy applications
• Real-time signal processing or complex algorithm execution on energy-constrained hardware
• Accelerators in data centers or cloud infrastructure for workloads that benefit from instruction reuse and parallel execution
• Multithreaded applications in systems-on-chip (SoC)
• Scientific computing or simulations with demand for high throughput per watt

BenefitsContent extracted from patent full text and abstract with AI.

• Significantly reduces instruction fetching, reusing instructions within processor elements to save energy and improve efficiency.
• Supports highly parallel and multithreaded computing, making it suitable for demanding workloads.
• Decentralized execution model minimizes control overhead, enabling lower-power operation compared to conventional CPUs.
• Dynamic allocation and eviction of execution fragments allow efficient management of hardware resources and scaling of performance.
• Instruction set and microarchitecture are designed for simplicity, making programming, compilation, and scaling easier without knowledge of array structure.
• Flexible architecture can be expanded or adapted for different performance, area, and power targets.
• Compared to traditional RISC-V and other similar systems, this approach can achieve 40% lower per-cycle switching activity, reducing overall energy consumption.
• Efficient handling of subroutines, coroutines, and asynchronous tasks via message passing and instance management.

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

A processing element array of a processor, comprising a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses. Also, a fabric cell or tile of a processor, comprising such a processing element array, an S bus that constitutes the data bus, and a cell or tile interface node. The interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; and the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.