Sigma-delta Modulator Comprising Digital-To-Analog Converter Error Correction

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This patent describes a method and system for significantly reducing errors caused by non-linearity in digital-to-analog converters (DACs) used within sigma-delta modulators. The invention continually monitors the digital input signals to the DAC for specific types of transitions (such as low-to-high or high-to-low) and uses this historical information to compute digital correction values. These correction values are then used to compensate both for static errors (from component mismatches) and dynamic, transition-related errors, resulting in a much more accurate output signal.

Use CasesContent extracted from patent full text and abstract with AI.

• High-fidelity audio and video processing systems that require precise digital-to-analog conversion.
• Measurement and instrumentation equipment where accurate analog signal generation from digital data is critical.
• Communication systems (such as wireless and wired transceivers) that use sigma-delta modulators for digital-to-analog signal conversion.
• Advanced data acquisition systems relying on high-resolution, low-noise DACs.
• Medical devices such as imaging equipment or patient monitoring systems that require precise analog outputs from digital systems.

BenefitsContent extracted from patent full text and abstract with AI.

• Dramatically improves signal accuracy by compensating for both static and dynamic DAC errors.
• Enables higher signal-to-noise ratios, leading to better performance in critical applications (e.g., from 84 dB to 107 dB as described).
• Reduces distortion and noise introduced by DAC non-linearities, enhancing overall system performance.
• Allows for real-time, adaptive error correction by analyzing ongoing signal transitions, leading to consistent performance despite component aging or changes.
• Can be implemented in both analog and digital output systems, offering broad applicability across various electronic devices.

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Patent Abstract

An embodiment of the invention relates to a method of operating a system comprising a digital-to-analog-converter (18), wherein an output signal (yout(t), yout(n)) of the system is improved by completely or at least partly compensating a non-linearity error of the digital-to-analog-converter (18), said method comprising the steps of: determining an error value (X1, X2, X3, Xn, X 1,LH , X 1,ST , X 1,HL , X 2,LH , X 2,ST , X 2,HL , X N,LH , X N,ST , X N,HL ) that quantifies the deficiency of at least one weight (g1-gN) of the digital-to-analog-converter (18), determining a digital correction value (yc(n)) based on said error value, and completely or at least partly compensating the non-linearity error of the digital-to-analog-converter (18) on the basis of the digital correction value (yc(n)). The embodiment is further characterized in that a digital input signal (y(n)), that itself forms the input signal of the digital-to-analog-converter (18) or at least shows the same signal transitions (LH, ST, HL) over time as the input signal of the digital-to-analog-converter (18), is analyzed regarding a signal transition (LH, ST, HL) or signal transitions (LH, ST, HL) in the past. The step of determining the digital correction value (yc(n)) includes taking into account whether or not a signal transition (LH, ST, HL) or signal transitions (LH, ST, HL) have taken place in the past.