Design Tool for the Type and Form of a Circuit Production

Publication: WO2008135596A2
Published: 2008-11-13
Family Size: 5
Granted: Yes (1/5)

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent discloses a design tool and method for circuit production, enabling designers to quickly select optimal circuit layouts and integration technologies for electronic or integrated circuit assemblies. By storing a large number of pre-computed design solutions in a database—each characterized by properties like integration technique, physical size, layer count, and wiring length—the tool allows users to compare, filter, and choose the most suitable design for a given integration task using interactive visual elements (e.g., display panels and controls). This approach streamlines the design process, shifts evaluation to a higher level of abstraction, and allows for effective trade-off analysis across multiple criteria and technologies.

Use CasesContent extracted from patent full text and abstract with AI.

  • Designing printed circuit boards (PCBs) for consumer electronics, automotive, industrial, or medical devices.
  • Optimization and selection of integrated circuit (IC) layouts, System-in-Package (SiP), Multichip Modules (MCM), and Chip-on-Board (CoB) for various electronic products.
  • Educational and research environments where comparing different integration technologies and design trade-offs is valuable.
  • Rapid prototyping and evaluation of alternative circuit production methods to minimize time-to-market.
  • Constraint management and multi-criteria decision-making in high-speed or high-density electronic system designs.

BenefitsContent extracted from patent full text and abstract with AI.

  • Significantly reduces design time and number of iterations needed for circuit layout and integration decisions.
  • Enables direct comparison between many pre-computed, pareto-optimal alternatives rather than sequential, time-consuming redesigns.
  • Supports filtering and interactive selection based on multiple technical properties (e.g., technology type, size, layers, wiring length, constraints), enabling efficient trade-off analysis.
  • Promotes higher-quality design outcomes by allowing selection of the best fit for complex integration tasks.
  • Facilitates management of conflicting constraints (e.g., design rules, signal integrity, thermal management) and supports global and local optimization.
  • Applicable across a wide variety of integration technologies and circuit types, including hybrid and embedded approaches, thus increasing flexibility and applicability for diverse electronic design challenges.

Technical Classifications (CPCs)

Main Classifications

Physics & Measurement

Sub Classifications

Computing & Calculating

CPC Codes

G06F30/30

Inventors & Applicants

Applicants

Fraunhofer Ges Forschung

Univ Berlin Tech

Schroeder Michael

Kuefer Karl-heinz

Polityko Dmitry-david

Patent Abstract

The invention relates to a method for influencing a selection for the "type and form of a circuit production" in at least one layer (L1, L2) for a given integration task for an integrated circuit or multiples thereof in a wafer composite, an assembly on a planar substrate or a compact assembly. A number of electrical or electronic components are thus arranged in three dimensions and are to be electrically connected together. A number of ready solutions (5; 5a, 5b) are retained in a databank (10) and each of the ready solutions has a group of properties, each group having at least the following properties for the given integration task: an integration technique, a housing or assembly size, a number of layers (physical planes) for conductor tracks or lines in a vertical direction and a line or conductor track length. The ready solutions (5) stored in the databank (10) for the given integration task define a target space (40), from which a solution (5b) may be selected using operating elements (21, 22) which fixes the type and form of the circuit production resulting from the given integration task and the number of electrical and electronic components in one of many integration techniques. The design time can thus be reduced.

Key Information

Publication No.

WO2008135596A2

Family ID

39944064

Publication Date

2008-11-13

Application No.

EP2008055658W

Application Date

2008-05-07

Priority Date

2007-05-08

Granted

Yes (1/5)

Possible Cooperation

For further information please contact the transfer office.