Method for Contacting and Packetising a Semiconductor Chip
Simple SummaryContent extracted from patent full text and abstract with AI.
This invention describes a method for electrically connecting (contacting) and packaging a semiconductor chip, particularly for power electronic components, using a 3D multi-material printing process. The method involves printing a lower contact layer, placing the semiconductor chip on it, printing a ceramic insulation layer around the chip, and then printing an upper contact layer. Thermal sintering is used to finish the assembly. This creates a compact, thermally efficient, and robust power semiconductor package with customizable structure.
Use CasesContent extracted from patent full text and abstract with AI.
- Manufacture of power semiconductor devices such as MOSFETs, IGBTs, and power modules
- Integration of electronic switching components in automotive electronics
- Production of compact and thermally optimized power supplies and inverters
- Fabrication of custom semiconductor packages for industrial automation and renewable energy systems
- Rapid prototyping of semiconductor power components using additive manufacturing
BenefitsContent extracted from patent full text and abstract with AI.
- Simplified and automated assembly process using 3D multi-material printing
- High thermal conductivity due to ceramic insulation, enabling better heat dissipation
- Improved electrical connection quality on both sides of the chip
- Customizable package designs, including easy incorporation of additional contacts and cooling features
- Reduced production costs and increased flexibility compared to traditional semiconductor packaging methods
Technical Classifications (CPCs)
Main Classifications
Electrical & Electronic Tech
Sub Classifications
Semiconductor & Solid-State Devices
CPC Codes
Inventors & Applicants
Applicants
Univ Chemnitz Tech
Patent Abstract
The invention relates to a method for contacting a semiconductor chip of a power-electronic component. The power-electronic component has a first lower contact face (1) and a semiconductor chip (2) positioned thereon, wherein a ceramic insulation layer (3), which extends over the first contact face not covered by the semiconductor chip and which surrounds the semiconductor along its circumference, is pressed onto the lower contact face, and a second upper contact face (4) is pressed onto the semiconductor chip.
Key Information
Publication No.
WO2019161833A1
Family ID
65818124
Publication Date
2019-08-29
Application No.
DE2019100092W
Application Date
2019-01-29
Priority Date
2018-02-23
Granted
Yes (2/6)
Possible Cooperation
For further information please contact the transfer office.