Circuit Arrangement and Method for Controlling the Gate of a Depletion Layer Field-Effect Transistor

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This invention introduces a circuit arrangement and method for controlling the gate of a depletion layer field-effect transistor (JFET), particularly for use in power electronics. It uses a current supply device (such as a constant current source) connected to the transistor gate, a switch to optionally short-circuit the current source, and a charge storage device (such as a capacitor) that can be connected in parallel. This setup is designed to guarantee reliable and fast switching of JFETs, avoiding accidental switching due to Miller effect and minimizing circuit complexity, without the need for elaborate measurement or control systems.

Use CasesContent extracted from patent full text and abstract with AI.

• Power electronic converters (inverters and matrix converters) using JFETs, especially SiC-based devices
• Gate driver circuits for high-efficiency power transistors in industrial and renewable energy systems
• Electronic switching applications requiring fast and safe turn-off behavior for normally-on JFETs
• Automotive power modules and motor drives where reliable gate control is critical
• Replacement of more complex or failure-prone MOSFET or IGBT gate drivers in specific power circuit topologies

BenefitsContent extracted from patent full text and abstract with AI.

• Ensures safe and secure turn-off of JFETs without requiring individual voltage tuning for each device
• Mitigates Miller effect and prevents unwanted reactivation (false switching) of transistors, thus avoiding short circuits
• Reduces circuit complexity and cost by removing need for additional measurement or regulation circuitry
• Enables fast and reliable switching operation, improving the efficiency of power electronic systems
• Compatible with both n-channel and p-channel JFETs and suitable for high-power applications
• Capacitor-assisted fast turn-off improves switching dynamics and reduces energy losses
• Simplifies adaptation in advanced converter technologies (such as matrix converters) that involve complex switching sequences

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Inventors & Applicants

Patent Abstract

A gate control device comprises a current supply device (551), which may be electrically coupled to a gate connector (303) and a source/drain connector (301) of a depletion layer field-effect transistor (300). The gate control device further comprises a switch device (552) for the optional short-circuiting of the current supply device (551) and a charge storage device (554) which is or may be connected in parallel to the current supply device (551). In a method for control of a depletion layer field-effect transistor, an electric current for the depletion layer field-effect transistor is generated in a first operating state such that the depletion layer field-effect transistor is operated in the channeling region. In a second operating state of the depletion layer field-effect transistor, electric charge is buffered, wherein at least a part of the buffered electric charge is generated in the first operating state of the depletion layer field-effect transistor.