Condensor and Method for Manufacturing the Same

Publication: EP3024033A1
Published: 2016-05-25
Family Size: 8
Granted: Yes (2/8)

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent discloses a method for manufacturing monolithic integrated capacitors (such as trench capacitors) with high capacitance density and high voltage resistance. The method involves building the dielectric structure inside a trench of a semiconductor substrate using multiple adjacent dielectric layers that have opposing mechanical stresses. By selecting materials and thicknesses with opposite stress characteristics, this technique significantly reduces or compensates for wafer bending during the manufacturing process, enabling the fabrication of dense, high-voltage capacitors that remain manufacturable and reliable.

Use CasesContent extracted from patent full text and abstract with AI.

  • Power electronics modules requiring high-voltage, high-capacitance integrated capacitors (e.g., industrial and automotive inverters or converters)
  • Semiconductor devices where integrated capacitors function as buffers, snubbers, or coupling elements placed on the same chip as other power switches (like MOSFETs or IGBTs)
  • Advanced memory chips requiring high-density capacitors in space-constrained designs
  • Integration into compact, high-performance circuit boards to reduce parasitics and improve thermal management
  • Use in AC/DC or DC/DC converters, inverters, and other power supply circuits demanding compact, robust capacitive components

BenefitsContent extracted from patent full text and abstract with AI.

  • Allows fabrication of high-density, high-voltage integrated capacitors without excessive wafer warpage, thus increasing production yield and device reliability
  • Supports higher capacitance and voltage ratings in a smaller chip area, reducing system size and cost
  • Improves mechanical stability of the wafer, which is crucial for further processing steps and industrial-scale manufacturing
  • Enables on-chip integration of capacitors with power semiconductor devices, minimizing connection inductance and enhancing electrical performance
  • Provides better thermal dissipation and predictable, stable capacitance across temperature, voltage, and frequency ranges

Technical Classifications (CPCs)

Main Classifications

Electrical & Electronic Tech

Sub Classifications

Electric Elements

Semiconductor & Solid-State Devices

CPC Codes

H01L21/78H10D1/047H10D1/665

Inventors & Applicants

Applicants

Fraunhofer Ges Forschung

Friedrich Alexander Universität Erlangen Nürnberg

Patent Abstract

In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.

Key Information

Publication No.

EP3024033A1

Family ID

54703823

Publication Date

2016-05-25

Application No.

EP15195837A

Application Date

2015-11-23

Priority Date

2014-11-24

Granted

Yes (2/8)

Possible Cooperation

For further information please contact the transfer office.