Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark

Publication: EP1835425A1
Published: 2007-09-19
Family Size: 6
Granted: Yes (3/6)

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent presents a technique for embedding a digital watermark into electronic circuits, especially IP cores within FPGAs or ASICs, by generating a unique, detectable signal on the circuit's power supply line. The watermark is stored in a memory component and, during a specific mode (or continuously), a signal generator outputs a distinctive voltage pattern based on this watermark. The watermark can then be detected by measuring the circuit's power supply (e.g., using an oscilloscope) and identifying the unique signature via signal analysis, thus verifying authenticity and ownership without extra hardware.

Use CasesContent extracted from patent full text and abstract with AI.

  • Protecting intellectual property in IP cores used in FPGAs and ASICs by embedding detectable watermarks.
  • Facilitating licensing enforcement for IP core suppliers, ensuring that unauthorized copies can be proven.
  • Enabling forensic analysis of hardware to confirm the authenticity of integrated circuits in supply chains.
  • Detecting unauthorized copying or modification of electronic circuit designs in embedded and industrial systems.
  • Providing non-invasive verification for circuit provenance and brand protection in high-value electronics.

BenefitsContent extracted from patent full text and abstract with AI.

  • Non-invasive detection: The watermark can be verified by simply measuring the power supply, without requiring access to internal design files or proprietary bitstreams.
  • Difficult to remove: The watermark is tightly integrated into the core’s functional logic, making it hard to erase without affecting normal circuit operation.
  • Works with encrypted bitstreams: Unlike many other approaches, this method allows for watermark detection even if the device’s configuration is encrypted.
  • Minimal hardware overhead: Only small additional logic is required to generate and embed the watermark signal.
  • Broad applicability: Can be used with a wide range of electronic circuits, including FPGAs, ASICs, and IP cores at various design stages.
  • Supports proof of ownership: Provides a practical way to demonstrate and enforce IP rights in legal or commercial disputes.

Technical Classifications (CPCs)

Main Classifications

Physics & Measurement

Sub Classifications

Computing & Calculating

CPC Codes

G06F21/73G06F21/76G06F21/81G06F30/30

Inventors & Applicants

Applicants

Fraunhofer Ges Forschung

Univ Friedrich Alexander Er

Patent Abstract

A watermarking apparatus for an electronic circuit is described, which comprises the following features: a watermark memory (110) operative to store a watermark (112) characterizing said electronic circuit, and a watermarking signal generator (120) operative to generate based on said watermark (112) a watermarking signal (122) on a power supply line (140) of said electronic circuit, wherein said watermarking signal (122) is detectable for a recognition of said watermark (112).

Key Information

Publication No.

EP1835425A1

Family ID

36218253

Publication Date

2007-09-19

Application No.

EP06005526A

Application Date

2006-03-17

Priority Date

2006-03-17

Granted

Yes (3/6)

Possible Cooperation

For further information please contact the transfer office.