Logic Chip, Logic System and Method for Designing a Logic Chip

Simple SummaryContent extracted from patent full text and abstract with AI.

This patent introduces a logic chip architecture, particularly suited for FPGAs, that features a configurable and highly flexible communication bar—essentially a reconfigurable on-chip bus—spanning multiple individually addressable logic blocks (resource blocks). Each resource block can either simply pass signals through the bus (bypass mode) or actively access and process signals from the bus (access mode, supporting read, write, or read/write). Interface locations between bus segments are uniform and standardized, allowing seamless module relocation, dynamic reconfiguration, and the integration of various-sized logic modules without communication bottlenecks or significant logic overhead. The methods and systems also include efficient ways to manage configuration and real-time adaptation based on system needs.

Use CasesContent extracted from patent full text and abstract with AI.

• Dynamic hardware reconfiguration in FPGA-based systems, such as adaptive communications, signal processing, or embedded control systems.
• Partial runtime reconfiguration—loading, removing, or relocating modules (e.g., IP cores) on hardware without halting system operation.
• Building customizable System-on-Chip (SoC) solutions where various hardware modules (e.g., audio/video processing, network acceleration, encryption) can be inserted, removed, or replaced as needed.
• Resource sharing and efficient hardware utilization in devices where constraints such as power, size, or cost are critical (e.g., mobile devices, aerospace, or automotive systems).
• Enabling hardware 'hot-plugging' concepts analogous to backplane buses (such as in industrial or telecom equipment), but on a chip, allowing modules to be swapped without system interruption.
• Prototyping and rapid system iteration for research, development, or field upgrades by swapping or updating function blocks in deployed equipment.

BenefitsContent extracted from patent full text and abstract with AI.

• Greatly increased flexibility in hardware design, enabling modules of different sizes/types to be freely placed and dynamically reconfigured on the chip.
• Significant reduction in communication logic and routing overhead due to unified, standardized bus interface locations, leading to more efficient use of chip resources.
• Support for both fixed and dynamic (runtime) reconfiguration without disturbing ongoing operations—ideal for systems requiring uptime or frequent hardware updates.
• Lower latency and higher bandwidth for on-chip communication compared to existing solutions, with support for multi-channel and streaming data (e.g., video, audio).
• Facilitation of modular design and easier IP reuse—designers can create independent modules that connect to a uniform bus, simplifying integration and scaling.
• Simpler development, testing, and field maintenance due to hardware linking and configuration management, which allows portions of hardware to be updated or replaced as easily as updating software.

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

A logic chip (1200) comprises a plurality of individually addressable resource blocks (1210, 1220) each of the resource blocks (1210, 1220) comprising logic circuitry (1216, 1226), and a communication bar (1212, 1222) extending across a plurality of the individually addressable resource blocks (1210, 1220). The communication bar comprises a plurality of communication bar segments (1212, 1222) associated with the resource slots (1210, 1220). The communication bar segments (1210, 1222) of the individually addressable resource blocks comprise identical interface locations (1214a, 1214b, 1224a, 1224b) with respect to boundaries of the resource blocks (1210, 1220), such that an input interface location (1214a) of a first resource block (1210) matches an output interface location (1224) of an adjacent second resource block (1220). At least one of the individually addressable resource blocks (1210; 1220) comprises a bypass segment (1212) of the communication bar. At least one of the individually addressable resource blocks (1210, 1220) comprises an access segment (1222) of the communication bar. The access segment (1222) comprises an access structure (1228) inserted between a first communication bar interface location (1224a) and a second communication bar interface location (1224b), to allow for a read access or a write access or a combined read/write access to the communication bar.