Interleaver

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This patent describes an improved interleaver for use with LDPC (Low-Density Parity-Check) encoded bit sequences. The invention segments the codeword into multiple chunks, with special treatment for error-correcting bits. It uses a hybrid approach: part block-wise and part random interleaving, specifically designed to enable more robust and effective decoding (via Belief Propagation) even when only limited channel state information is initially available. The structure allows the decoder to function reliably with shorter pilot (preamble) sequences, thus improving data throughput or robustness in noisy wireless channels.

Use CasesContent extracted from patent full text and abstract with AI.

• Wireless communication systems (e.g., 5G, Wi-Fi, DVB-NGH, IEEE 802.15.4w) using LDPC codes.
• IoT devices and low-power wide-area networks needing reliable communications over fading and noisy channels.
• Satellite communication systems employing LDPC codes for error correction.
• Any scenario where robust error correction is needed but preamble/pilot length must be minimized (e.g., high-throughput or power-constrained applications).
• Software-defined radios and modern communication chipsets implementing LDPC decoding.

BenefitsContent extracted from patent full text and abstract with AI.

• Enables LDPC decoding with limited or partial channel estimation, improving the probability of successful decoding from the start of transmission.
• Allows shorter pilot or preamble sequences, increasing the effective data rate or reducing beacon overhead.
• Enhances robustness to channel fading or erasures due to optimized distribution of error-correcting bits.
• Supports iterative channel estimation and decoding, further improving reliability in challenging wireless environments.
• The approach is compatible with existing LDPC standards with minimal changes required to encoding/decoding hardware or software.

Technical Classifications (CPCs)

Inventors & Applicants

Patent Abstract

Embodiments provide an interleaver for interleaving an LDPC encoded bit sequence, wherein the interleaver comprises a segmentation stage configured to segment the LDPC encoded bit sequence into a plurality of chunks, the plurality of chunks comprising a first chunk and one or more other chunks, a first interleaver stage, configured to interleave the one or more other chunks or a concatenated version thereof, a second interleaver stage, configured to block wise interleave the first chunk of the plurality of chunks and an interleaved bit sequence provided by the first interleaver stage, to obtain an interleaved version of the LDPC encoded bit sequence, wherein the first chunk of the plurality of chunks consists of bits of a first type, wherein the bits of the first type are error correcting bits of the LDPC encoded bit sequence, are repeat accumulate bits of the LDPC encoded bit sequence, and/or are represented, in a Tanner graph representation of the LDPC encoded bit sequence, by variable nodes that comprise non-random connections to at least two error correcting check nodes.